Solid state image sensors include those incorporating complementary metal oxide semiconductor (CMOS) design. A photodiode-based pixel array collects opto-electrons for imaging purposes. The pixels are arranged in a row-column format that may, for example, be a 1280×800 array. Row processing circuitry and column processing circuitry operate by known methods to pre-process analog signals and convert the analog signals to digital signals. Low voltage differential signaling (LVDS) provides the final digital output stage. See for example U.S. Pat. No. 7,483,058 issued to Frank et al. and U.S. Pat. No. 7,265,784 issued to Frank.
Designs for competitive imaging technologies include those for charge-coupled device (CCD) and CMOS imaging sensors. These concepts originated in the 1960 and 1970's. While CCD technology achieved an early lead, CMOS is now emerging as the dominant technology. The rise of CMOS-based imaging technology is, in part, attributable to new processing technologies that reduce the size of solid state transistors (MOSFET). Smaller transistor sizes provide higher density, faster speed, lower power dissipation, and more functionality that can be integrated on a single chip. This densification is shown by way of example where in 1995 Jet Propulsion Laboratory produces the first successful active 128×128 pixel CMOS image sensor. The distance from pixel to pixel is known as the pixel pitch. The JPL device of 1995 had a pixel pitch of about 20 μm. This compares to current technologies that are capable of shrinking the pixel pitch down to about 1.2 μm in fully functional imaging devices; however, transistor size is no longer the limiting factor in achieving further scale reductions beyond about 1.2 μm.
Smaller pixel sizes problematically provide less photosensing area on the pixel itself. Each pixel is less sensitive to light where also the signal to noise ratio is disadvantageously reduced. These problems diminish the dynamic range that is achievable from each pixel. Various solutions have been proposed to address this problem, but each solution has its own problems. Logarithmic response pixels have been proposed to extend the dynamic range nonlinearly, as reported in Kavidas et al. “a Logarithmic Response CMOS Image Sensor With On-Chip Calibration” IEEE Journal of Solid State Circuits, Vol. 35, No. 8 pp. 1146-1152 (August 2000). This solution is problematic where the nonlinear response produces difficulty in reconstructing the final image. Another proposed solution is to provide a lateral overflow capacitor as reported in Akahane et al., “A Sensitivity and Linearity Improvement of a 100-dB Dynamic Range CMOS Image Sensor Using A Lateral Overflow Integration Capacitor” IEEE Journal of Solid State Circuits, Vol. 41 No. 7, pp. 1577-1587 (July 2008). This second solution problematically introduces a large variation in the threshold voltage of the transfer gates, and this may introduce additional ‘dark’ current leading to higher dark current imaging shot noise. Some have proposed adopting multiple exposure times to expand the dynamic range as reported in Mase et al. “A Wide Dynamic Range CMOS Image Sensor With Multiple Exposure-Time Signal Outputs and 12-bit Column-Parallel Cyclic A/D Converters” IEEE Journal of Solid-State Circuits, Vol. 40 No. 12 pp. 2787-2795 (December 2005). This third solution produces discontinuity in the signal-to-noise ratio, where also differing integration times may distort images due to motion.
As reported in U.S. Pat. No. 5,625,210 issued to Lee et al., pinned photodiodes may be incorporated into CMOS image sensors to improve the blue response, reduce image lag and minimize the dark current characteristics of active pixel sensors.